CDC857-2DGGG4

Mfr. #:: CDC857-2DGGG4
説明:: IC 2.5V PLL CLK-DRVR 48-TSSOP
ライフサイクル:: メーカー新製品
データシート:: CDC857-2DGGG4 データシート
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詳しくは:: CDC857-2DGGG4 詳しくは CDC857-2DGGG4 Product Details

製品属性
属性値

メーカー: テキサスインスツルメンツ

製品カテゴリ: クロック/タイミング-クロックジェネレータ、PLL、周波数シンセサイザ

シリーズ: -

タイプ: PLLクロックドライバー

包装: チューブ代替包装

パッケージ-ケース: 48-TFSOP (0.240", 6.10mm Width)

作動温度: 0°C ~ 85°C

取付タイプ: 表面実装

電圧供給: 2.3 V ~ 2.7 V

サプライヤー-デバイス-パッケージ: 48-TSSOP

PLL: はいバイパスあり

入力: LVTTL, SSTL-2

出力: SSTL-2

回路数: 1

比率-入力：出力: 1899/12/30 1:10:00

差動入力：出力: はいはい

周波数-最大: 167MHz

除算器-乗数: いいえ/いいえ

Tags: CDC857-2D, CDC857-2, CDC85, CDC8, CDC

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We provide 90-360 days warranty.

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CDC857-2DGGG4 説明

***ical: PLL Clock Driver Single 66MHz to 167MHz 48-Pin TSSOP Tube

***ark: IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:2.3V to 2.7V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes

***as Instruments: The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.

Market price

モデル	説明	ストック	価格
CDC857-2DGGG4 DISTI # CDC857-2DGGG4-ND	IC 2.5V PLL CLK-DRVR 48-TSSOP RoHS: Compliant Min Qty: 40 Container: Tube	Limited Supply - Call
CDC857-2DGGG4 DISTI # CDC857-2DGGG4	PLL Clock Driver Single 66MHz to 167MHz 48-Pin TSSOP Tube - Rail/Tube (Alt: CDC857-2DGGG4) RoHS: Compliant Min Qty: 1000 Container: Tube	Americas - 0
CDC857-2DGGG4 DISTI # 595-CDC857-2DGGG4	Clock Drivers & Distribution Phase-Lock Loop Clock Drivers RoHS: Compliant	0
CDC857-2DGGG4	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48 RoHS: Compliant	20	1000:$14.7000 500:$15.4700 100:$16.1100 25:$16.8000 1:$18.0900

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