SN74ALVC7813-40DL

SN74ALVC7813-40DL
Mfr. #:
SN74ALVC7813-40DL
説明:
FIFO 16-Bit Buffer/Driver With 3-State Outputs
ライフサイクル:
メーカー新製品
データシート:
SN74ALVC7813-40DL データシート
配達:
DHL FedEx Ups TNT EMS
支払い:
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ECAD Model:
詳しくは:
SN74ALVC7813-40DL 詳しくは SN74ALVC7813-40DL Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
FIFO
JBoss:
Y
データバス幅:
18 bit
バスの方向:
一方向
メモリー容量:
1.125 kbit
タイミングタイプ:
同期
組織:
64 k x 18
回路数:
2
最大クロック周波数:
25 MHz
アクセス時間:
20 ns
供給電圧-最大:
3.6 V
供給電圧-最小:
3 V
供給電流-最大:
0.04 mA
最低動作温度:
0 C
最高作動温度:
+ 70 C
パッケージ/ケース:
SSOP-56
包装:
チューブ
高さ:
2.59 mm
幅:
7.49 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
動作供給電圧:
3 V to 3.6 V
製品タイプ:
FIFO
ファクトリーパックの数量:
1
サブカテゴリ:
メモリとデータストレージ
単位重量:
0.024508 oz
Tags
SN74ALVC7813, SN74ALVC781, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP Tube
***pNet
FIFO Mem Dual Width Uni-Dir 64 x 18 56-Pin SSOP
***i-Key
IC 64X18 SYNC FIFO MEM 56-SSOP
***as Instruments
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET\) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.
モデル 説明 ストック 価格
SN74ALVC7813-40DL
DISTI # 296-5171-5-ND
IC 64X18 SYNC FIFO MEM 56-SSOP
RoHS: Compliant
Min Qty: 80
Container: Tube
Limited Supply - Call
    SN74ALVC7813-40DLR
    DISTI # SN74ALVC7813-40DLR-ND
    IC MEMORY FIFO 64X18 56-SSOP
    RoHS: Compliant
    Min Qty: 1000
    Container: Tape & Reel (TR)
    Limited Supply - Call
      SN74ALVC7813-40DL
      DISTI # 595-SN74ALVC781340DL
      FIFO 16-Bit Buffer/Driver With 3-State Outputs
      RoHS: Compliant
      0
        SN74ALVC7813-40DLR
        DISTI # 595-SN74ALVC7813-40D
        FIFO 64 x 18 3.3-V Synch FIFO Memory
        RoHS: Compliant
        0
          SN74ALVC7813-40DLFIFO, 64X18, 20ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant
          1494
          • 1000:$5.7800
          • 500:$6.0800
          • 100:$6.3300
          • 25:$6.6000
          • 1:$7.1100
          SN74ALVC7813-40DLRFIFO, 64X18, 20ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant
          1000
          • 1000:$5.7800
          • 500:$6.0800
          • 100:$6.3300
          • 25:$6.6000
          • 1:$7.1100
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          可用性
          ストック:
          Available
          注文中:
          1000
          数量を入力してください:
          SN74ALVC7813-40DLの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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