SN74LVC823ANSR

SN74LVC823ANSR
Mfr. #:
SN74LVC823ANSR
説明:
Flip Flops 9-Bit Bus Intfc FlipFlop W/3-St Otpt
ライフサイクル:
メーカー新製品
データシート:
SN74LVC823ANSR データシート
配達:
DHL FedEx Ups TNT EMS
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ECAD Model:
詳しくは:
SN74LVC823ANSR 詳しくは SN74LVC823ANSR Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
ビーチサンダル
JBoss:
Y
回路数:
1
ロジックファミリ:
74LV
ロジックタイプ:
バスインターフェースフリップフロップ
極性:
非反転
入力方式:
シングルエンド
出力タイプ:
シングルエンド
伝播遅延時間:
8.9 ns
高レベル出力電流:
- 24 mA
低レベル出力電流:
24 mA
供給電圧-最小:
1.65 V
供給電圧-最大:
3.6 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
取り付けスタイル:
SMD / SMT
パッケージ/ケース:
SO-24
包装:
リール
関数:
Dタイプバスインターフェース
高さ:
1.95 mm
長さ:
15 mm
静止電流:
10 uA
幅:
5.3 mm
ブランド:
テキサスインスツルメンツ
チャネル数:
9
入力行数:
9
出力ラインの数:
3
動作供給電圧:
1.65 V to 3.6 V
製品タイプ:
ビーチサンダル
リセットタイプ:
マスターリセット
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
単位重量:
0.010857 oz
Tags
SN74LVC823, SN74LVC82, SN74LVC8, SN74LVC, SN74LV, SN74L, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Driver, LVC/LCX/Z Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24
***i-Key
IC D-TYPE POS TRG SNGL 24SO
***el Nordic
Contact for details
***as Instruments
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN)\ input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR)\ input low causes the nine Q outputs to go low, independently of the clock. A buffered output-enable (OE)\ input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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可用性
ストック:
Available
注文中:
3500
数量を入力してください:
SN74LVC823ANSRの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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