SN74ABT16853DLG4

SN74ABT16853DLG4
Mfr. #:
SN74ABT16853DLG4
説明:
Bus Transceivers Dual 8 To 9-Bit Prty Transceivers
ライフサイクル:
メーカー新製品
データシート:
SN74ABT16853DLG4 データシート
配達:
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ECAD Model:
詳しくは:
SN74ABT16853DLG4 詳しくは SN74ABT16853DLG4 Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
バストランシーバー
JBoss:
Y
ロジックファミリ:
74ABT
入力レベル:
TTL
出力レベル:
TTL
出力タイプ:
3-State or Open Collector
高レベル出力電流:
- 32 mA
低レベル出力電流:
64 mA
伝播遅延時間:
3.9 ns
供給電圧-最大:
5.5 V
供給電圧-最小:
4.5 V
最低動作温度:
- 40 C
最高作動温度:
+ 85 C
パッケージ/ケース:
SSOP-56
包装:
チューブ
関数:
パリティチェッカー付きバストランシーバー
高さ:
2.59 mm
長さ:
18.41 mm
回路数:
2
製品:
BiCMOS
静止電流:
32 mA
テクノロジー:
BiCMOS
幅:
7.49 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
チャネル数:
16
供給電流-最大:
40 mA
動作供給電圧:
4.5 V to 5.5 V
極性:
非反転
製品タイプ:
バストランシーバー
ファクトリーパックの数量:
1
サブカテゴリ:
ロジックIC
単位重量:
0.024508 oz
Tags
SN74ABT16853DL, SN74ABT1685, SN74ABT168, SN74ABT16, SN74ABT1, SN74AB, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***eco
8-TO-9 BIT PARITY BUS TRANSCEIVER<AZ
***i-Key
IC TXRX BUS 8-9BIT DUAL 56-SSOP
***ark
Transceiver Logic IC; Logic Family:ABT; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:56-SSOP; No. of Pins:56; Operating Temperature Range:-40°C to +85°C; Input Type:TTL; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
The 'ABT16853 dual 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus, with its corresponding parity bit, the open-collector parity-error () output indicates whether or not an error in the B data has occurred. The output-enable (and ) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT16853 provide true data at the outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When both and are low, data is transferred from the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16853 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16853 is characterized for operation from -40°C to 85°C.
モデル 説明 ストック 価格
SN74ABT16853DLG4
DISTI # SN74ABT16853DLG4-ND
IC TXRX NON-INVERT 5.5V 56SSOP
RoHS: Compliant
Min Qty: 80
Container: Tube
Limited Supply - Call
    SN74ABT16853DLG4
    DISTI # 595-SN74ABT16853DLG4
    Bus Transceivers Dual 8 To 9-Bit Prty Transceivers
    RoHS: Compliant
    0
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      可用性
      ストック:
      Available
      注文中:
      4000
      数量を入力してください:
      SN74ABT16853DLG4の現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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