SN74ACT3641-30PQ

SN74ACT3641-30PQ
Mfr. #:
SN74ACT3641-30PQ
説明:
FIFO 1024 x 36 synch FIFO Memory
ライフサイクル:
メーカー新製品
データシート:
SN74ACT3641-30PQ データシート
配達:
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ECAD Model:
詳しくは:
SN74ACT3641-30PQ 詳しくは SN74ACT3641-30PQ Product Details
製品属性
属性値
メーカー:
テキサスインスツルメンツ
製品カテゴリ:
FIFO
JBoss:
Y
データバス幅:
36 bit
バスの方向:
双方向
メモリー容量:
36 kbit
タイミングタイプ:
同期
組織:
1 k x 36
回路数:
2
最大クロック周波数:
33.4 MHz
アクセス時間:
15 ns
供給電圧-最大:
5.5 V
供給電圧-最小:
4.5 V
供給電流-最大:
0.4 mA
最低動作温度:
0 C
最高作動温度:
+ 70 C
パッケージ/ケース:
BQFP-132
包装:
チューブ
高さ:
3.56 mm
幅:
24.13 mm
ブランド:
テキサスインスツルメンツ
取り付けスタイル:
SMD / SMT
感湿性:
はい
動作供給電圧:
5 V
製品タイプ:
FIFO
ファクトリーパックの数量:
1
サブカテゴリ:
メモリとデータストレージ
単位重量:
0.162567 oz
Tags
SN74ACT364, SN74ACT36, SN74ACT3, SN74ACT, SN74AC, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Depth Bi-Dir 1K x 36 132-Pin BQFP Tray
***i-Key
IC CLOCKED FIFO MEMORY 132-QFP
***as Instruments
The SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 12 ns. The 1024 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices are used in parallel to create wider datapaths. Expansion is also possible in word depth. The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the AF\ and AE\ flags of the FIFO can be programmed from port A or through a serial input. The SN74ACT3641 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)
モデル 説明 ストック 価格
SN74ACT3641-30PQ
DISTI # 296-4413-ND
IC CLOCKED FIFO MEMORY 132-QFP
RoHS: Compliant
Min Qty: 36
Container: Tray
Limited Supply - Call
    SN74ACT3641-30PQ
    DISTI # 595-SN74ACT3641-30PQ
    FIFO 1024 x 36 synch FIFO Memory
    RoHS: Compliant
    0
      SN74ACT3641-30PQBi-Directional FIFO, 1KX36, 15ns, Synchronous, CMOS, PQFP132
      RoHS: Compliant
      278
      • 1000:$25.4100
      • 500:$26.7500
      • 100:$27.8400
      • 25:$29.0400
      • 1:$31.2700
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      可用性
      ストック:
      Available
      注文中:
      1000
      数量を入力してください:
      SN74ACT3641-30PQの現在の価格は参考用です。最高の価格をご希望の場合は、お問い合わせまたは直接メールで営業チーム[email protected]までご連絡ください。
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