By Lattice Semiconductor Corporation 18
Building off its broad support for bridging image sensors to parallel buses for ISP (Image Signal Processors), Lattice has designed a sensor interface board. The MachXO2 Dual Sensor Interface Board (DSIB) demonstrates two image sensors being merged into one parallel stream for an ISP to process the combined image.
The NanoVesta Head Board comprises a compact, low cost, high dynamic range (HDR) image sensor, lens and lens housing with adjustable focus, that can bolt directly onto the Lattice HDR-60 base board. Both the NanoVesta and HDR-60 boards have been designed to work together as part of the Lattice HDR-60 video camera development kit. The NanoVesta head board is designed to use the Aptina MT9M023 1/3-inch CMOS digital image sensor.
The Lattice HDR-60 Video Camera Development Kit is a production ready High Dynamic Range (HDR) camera, designed to fit into commercially available camera housings. The hardware is designed to support full 1080p resolution at 60 frames per second in streaming mode through the FPGA, without the need for any external frame buffer. The integrated 'IONOS' Image Signal Processing (ISP) IP pipeline from Lattice partner, Helion GmbH, provides end-to-end ISP support from sensor to displayable image, and incorporates sensor interfacing, defective pixel correction and 2D noise reduction, high quality 5 x 5 DeBayer, Color Correction Matrix, Fast Auto Exposure, Auto White Balance, HDR, Gamma Correction and Overlay (both character and graphics). Lattice HDMI PHY IP enables output to HDMI/DVI monitors. The kit provides the industry's fastest Auto-Exposure, very high quality Auto White Balance and HDR greater than 120 dB. On board Broadcom Broadreach™ PHY enables support for Ethernet over coax up to a run length of 700 meters. The hardware supports up to 16-megapixel sensors, can support up to 2 sensors simultaneously and is easily programmable via standard low-cost USB cable.