SmartFusion® customizable System-on-Chips (cS

By Microsemi SoC 33

SmartFusion® customizable System-on-Chips (cS

Microsemi's SmartFusion family of SoCs builds on the technology first introduced with Fusion mixed-signal FPGAs. SmartFusion SoCs are made possible by integrating FPGA technology with programmable high-performance analog and hardened Arm® Cortex®-M3 microcontroller blocks on a Flash semiconductor process. The SmartFusion SoC takes its name from the fact that these three discrete technologies are integrated on a single chip, enabling low-cost ownership and small footprint solutions.

The MSS is composed of a 100 MHz Cortex-M3 processor and integrated peripherals, which are interconnected via a multi-layer AHB bus matrix (ABM). This matrix allows the Cortex-M3 processor, FPGA fabric master, Ethernet media access controller (MAC), when available, and peripheral DMA (PDMA) controller to act as masters to the integrated peripherals, FPGA fabric, embedded non-volatile memory (eNVM), embedded synchronous RAM (eSRAM), external memory controller (EMC), and analog compute engine (ACE) blocks. SmartFusion cSoCs of different densities offer various sets of integrated peripherals. Available peripherals include SPI, I2C, and UART serial ports, embedded FlashROM (EFROM), 10/100 Ethernet MAC, timers, phase-locked loops (PLLs), oscillators, real-time counters (RTC), and peripheral DMA controller (PDMA).

Features
  • Microcontroller subsystem (MSS)
    • Hardware industry-standard 100 MHz, 32-bit Arm Cortex-M3 CPU
    • Multi-layer AHB communication matrix with up to 16 Gbps throughput
    • 10/100 Ethernet MAC with RMII interface
    • Two of each: SPI, I2C, UART, 32-bit timers
    • Up to 512 KB Flash and 64 KB of SRAM
    • External memory controller (EMC)
    • 8-channel DMA controller
    • Up to 41 MSS I/Os with Schmitt trigger inputs
      • 25 I/Os can be used as FPGA I/Os
  • FPGA Fabric
    • Based on Microsemi’s proven ProASIC®3 architecture
    • 60,000 to 500,000 system gates with 350 MHz system performance
    • Up to 128 FPGA I/Os supporting LVDS, PCI, PCI-X, and LVTTL/LVCMOS standards
    • Embedded SRAMs and FIFOs
      • Variable aspect ratio 4,608-bit SRAM blocks
      • x1, x2, x4, x9, and x18 organizations
      • True dual-port SRAM (including x18)
  • Programmable Analog
    • High-performance analog signal conditioning blocks (SCB) with voltage, current and temperature monitors
    • Analog compute engine (ACE) offloads CPU from analog initialization and processing of analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), and SCBs
    • Integrated ADCs and DACs with 1 percent accuracy
    • 12-/10-/8-bit mode ADCs with 500/550/600 Ksps sampling rate
    • Up to ten 15 ns high-speed comparators
    • Up to 32 analog inputs and 3 outputs

カテゴリ

Top